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A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing.

C. Sudarshan, J. Lappas, C. Weis, D. Mathew, M. Jung, and N. Wehn. SAMOS, volume 11733 of Lecture Notes in Computer Science, page 429-441. Springer, (2019)

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Gertraud Lappas

Ingo Lappas

Marc Lappas

Georgios Lappas

Norbert Lappas

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Correction to: Efficient Hardware Architectures for 1D- and MD-LSTM Networks.V. Rybalkin, C. Sudarshan, C. Weis, J. Lappas, N. Wehn, and L. Cheng. J. Signal Process. Syst., 93 (12): 1467 (2021)A Novel DRAM Architecture for Improved Bandwidth Utilization and Latency Reduction Using Dual-Page Operation.C. Sudarshan, L. Steiner, M. Jung, J. Lappas, C. Weis, and N. Wehn. IEEE Trans. Circuits Syst. II Express Briefs, 68 (5): 1615-1619 (2021)A Weighted Current Summation Based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference.C. Sudarshan, T. Soliman, J. Lappas, C. Weis, M. Sadi, M. Jung, A. Guntoro, and N. Wehn. IEEE J. Emerg. Sel. Topics Circuits Syst., 12 (2): 367-380 (2022)Investigation of Pass Transistor Logic in a 12nm FinFET CMOS Technology.A. Chinazzo, J. Lappas, C. Weis, Q. Huang, Z. Wu, L. Ni, and N. Wehn. ICECS 2022, page 1-4. IEEE, (2022)Machine learning based soft error rate estimation of pass transistor logic in high-speed communication.Z. Zhang, J. Lappas, A. Chinazzo, C. Weis, Z. Wu, L. Ni, N. Wehn, and M. Tahoori. ETS, page 1-4. IEEE, (2022)An In-DRAM Neural Network Processing Engine.C. Sudarshan, J. Lappas, M. Ghaffar, V. Rybalkin, C. Weis, M. Jung, and N. Wehn. ISCAS, page 1-5. IEEE, (2019)A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing.C. Sudarshan, J. Lappas, C. Weis, D. Mathew, M. Jung, and N. Wehn. SAMOS, volume 11733 of Lecture Notes in Computer Science, page 429-441. Springer, (2019)Efficient Hardware Architectures for 1D- and MD-LSTM Networks.V. Rybalkin, C. Sudarshan, C. Weis, J. Lappas, N. Wehn, and L. Cheng. J. Signal Process. Syst., 92 (11): 1219-1245 (2020)Revisiting Pass-Transistor Logic Styles in a 12nm FinFET Technology Node.J. Lappas, A. Chinazzo, C. Weis, C. Xia, Z. Wu, L. Ni, and N. Wehn. DATE, page 1083-1084. IEEE, (2022)

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Disambiguation of "Lappas, Jan"

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A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing.

Please choose a person to relate this publication to

Gertraud Lappas

Ingo Lappas

Marc Lappas

Georgios Lappas

Norbert Lappas

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Lappas, Jan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing.

Please choose a person to relate this publication to

Gertraud Lappas

Ingo Lappas

Marc Lappas

Georgios Lappas

Norbert Lappas

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing.