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A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing.

C. Sudarshan, J. Lappas, C. Weis, D. Mathew, M. Jung, and N. Wehn. SAMOS, volume 11733 of Lecture Notes in Computer Science, page 429-441. Springer, (2019)

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Sudarshan Tiwari

Sudarshan Bahukudumbi

Sudarshan Malla

Sudarshan Baruah

Chirag Ashokkumar Jhala

Other publications of authors with the same name

Efficient Hardware Architectures for 1D- and MD-LSTM Networks.V. Rybalkin, C. Sudarshan, C. Weis, J. Lappas, N. Wehn, and L. Cheng. J. Signal Process. Syst., 92 (11): 1219-1245 (2020)Efficient Generation of Application Specific Memory Controllers.M. Natale, M. Jung, K. Kraft, F. Lauer, J. Feldmann, C. Sudarshan, C. Weis, S. Krumke, and N. Wehn. MEMSYS, page 233-247. ACM, (2020)Channel Models for Physical Unclonable Functions based on DRAM Retention Measurements.S. Müelich, S. Bitzer, C. Sudarshan, C. Weis, N. Wehn, M. Bossert, and R. Fischer. REDUNDANCY, page 149-154. IEEE, (2019)Optimization of DRAM based PIM Architecture for Energy-Efficient Deep Neural Network Training.C. Sudarshan, M. Sadi, C. Weis, and N. Wehn. ISCAS, page 1472-1476. IEEE, (2022)Efficient coding scheme for DDR4 memory subsystems.K. Kraft, D. Mathew, C. Sudarshan, M. Jung, C. Weis, N. Wehn, and F. Longnos. MEMSYS, page 148-157. ACM, (2018)ZuSE Ki-Avf: Application-Specific AI Processor for Intelligent Sensor Signal Processing in Autonomous DrivingG. Thieu, S. Gesper, G. Payá-Vayá, C. Riggers, O. Renke, T. Fiedler, J. Marten, T. Stuckenberg, H. Blume, C. Weis and 18 other author(s). 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), page 1-6. (April 2023)A Critical Assessment of DRAM-PIM Architectures - Trends, Challenges and Solutions.C. Sudarshan, M. Sadi, L. Steiner, C. Weis, and N. Wehn. SAMOS, volume 13511 of Lecture Notes in Computer Science, page 362-379. Springer, (2022)A Novel DRAM Architecture for Improved Bandwidth Utilization and Latency Reduction Using Dual-Page Operation.C. Sudarshan, L. Steiner, M. Jung, J. Lappas, C. Weis, and N. Wehn. IEEE Trans. Circuits Syst. II Express Briefs, 68 (5): 1615-1619 (2021)eBrainII: a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale Cortex.D. Stathis, C. Sudarshan, Y. Yang, M. Jung, C. Weis, A. Hemani, A. Lansner, and N. Wehn. J. Signal Process. Syst., 92 (11): 1323-1343 (2020)Correction to: Efficient Hardware Architectures for 1D- and MD-LSTM Networks.V. Rybalkin, C. Sudarshan, C. Weis, J. Lappas, N. Wehn, and L. Cheng. J. Signal Process. Syst., 93 (12): 1467 (2021)

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Disambiguation of "Sudarshan, Chirag"

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A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing.

Please choose a person to relate this publication to

Sudarshan Tiwari

Sudarshan Bahukudumbi

Sudarshan Malla

Sudarshan Baruah

Chirag Ashokkumar Jhala

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Sudarshan, Chirag"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing.

Please choose a person to relate this publication to

Sudarshan Tiwari

Sudarshan Bahukudumbi

Sudarshan Malla

Sudarshan Baruah

Chirag Ashokkumar Jhala

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing.