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Efficient Hardware Architectures for 1D- and MD-LSTM Networks.

, , , , , and . J. Signal Process. Syst., 92 (11): 1219-1245 (2020)

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iDocChip - A Configurable Hardware Architecture for Historical Document Image Processing: Text Line Extraction., , , , and . ReConFig, page 1-8. IEEE, (2019)Efficient Hardware Architectures for 1D- and MD-LSTM Networks., , , , , and . J. Signal Process. Syst., 92 (11): 1219-1245 (2020)iDocChip: A Configurable Hardware Architecture for Historical Document Image Processing., , , , , and . Int. J. Parallel Program., 49 (2): 253-284 (2021)When Massive GPU Parallelism Ain't Enough: A Novel Hardware Architecture of 2D-LSTM Neural Network., , , and . ACM Trans. Reconfigurable Technol. Syst., 15 (1): 2:1-2:35 (2022)Correction to: Efficient Hardware Architectures for 1D- and MD-LSTM Networks., , , , , and . J. Signal Process. Syst., 93 (12): 1467 (2021)Embedded Face Recognition for Personalized Services in the Assistive Robotics., , , , , , and . PKDD/ECML Workshops (1), volume 1524 of Communications in Computer and Information Science, page 339-350. Springer, (2021)Efficient hardware accleration of recurrent neural networks = Effiziente Hardwarebeschleunigung rekurrenter neuronaler Netze.. Kaiserslautern University of Technology, Germany, (2022)When Massive GPU Parallelism Ain't Enough: A Novel Hardware Architecture of 2D-LSTM Neural Network., and . FPGA, page 111-121. ACM, (2020)iDocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing., , , , , and . J. Imaging, 7 (9): 175 (2021)Real-Time Energy Efficient Hand Pose Estimation: A Case Study., , , , , , , and . Sensors, 20 (10): 2828 (2020)