Please log in to take part in the discussion (add own reviews or comments).
Cite this publication
More citation styles
- please select -
%0 Journal Article
%1 journals/vlsisp/RybalkinSWLWC20
%A Rybalkin, Vladimir
%A Sudarshan, Chirag
%A Weis, Christian
%A Lappas, Jan
%A Wehn, Norbert
%A Cheng, Li
%D 2020
%J J. Signal Process. Syst.
%K dblp
%N 11
%P 1219-1245
%T Efficient Hardware Architectures for 1D- and MD-LSTM Networks.
%U http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp92.html#RybalkinSWLWC20
%V 92
@article{journals/vlsisp/RybalkinSWLWC20,
added-at = {2021-07-25T00:00:00.000+0200},
author = {Rybalkin, Vladimir and Sudarshan, Chirag and Weis, Christian and Lappas, Jan and Wehn, Norbert and Cheng, Li},
biburl = {https://www.bibsonomy.org/bibtex/22fab330b0b1baa69e574149cf108a1eb/dblp},
ee = {https://doi.org/10.1007/s11265-020-01554-x},
interhash = {8803757a940f402366d2507855ce698a},
intrahash = {2fab330b0b1baa69e574149cf108a1eb},
journal = {J. Signal Process. Syst.},
keywords = {dblp},
number = 11,
pages = {1219-1245},
timestamp = {2024-04-09T03:12:00.000+0200},
title = {Efficient Hardware Architectures for 1D- and MD-LSTM Networks.},
url = {http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp92.html#RybalkinSWLWC20},
volume = 92,
year = 2020
}
