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Disambiguation of "Llabería, José María"

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MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array.

, , , , , , , , , , and . ICECS, page 1-5. IEEE, (2023)

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María José Carrascosa Gómez

María José Benítez Romero

María José Mendiburo Seguel

José María Navarro Adriaensens

José-Maria Hinz

 

Other publications of authors with the same name

Counteracting Bank Misprediction in Sliced First-Level Caches., , , and . Euro-Par, volume 2790 of Lecture Notes in Computer Science, page 586-596. Springer, (2003)An Enhancement for a Scheduling Logic Pipelined over two Cycles ., , , and . ICCD, page 203-209. IEEE, (2006)Increasing the Effective Bandwidth of Complex Memory Systems in Multivector Processors., and . SC, page 26. IEEE Computer Society, (1996)Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors., , , , , and . HPCA, page 191-202. IEEE Computer Society, (2003)A Mechanism for Verifying Data Speculation., , and . Euro-Par, volume 3149 of Lecture Notes in Computer Science, page 525-534. Springer, (2004)A performance evaluation of the multiple bus network for multiprocessor systems., , , , and . SIGMETRICS, page 200-206. ACM, (1983)Exploiting reuse locality on inclusive shared last-level caches., , , and . ACM Trans. Archit. Code Optim., 9 (4): 38:1-38:19 (2013)Performance evaluation of transputer systems with linear algebra problems., , , and . Microprocessing and Microprogramming, 32 (1-5): 825-832 (1991)Contents Management in First-Level Multibanked Data Caches., , , and . Euro-Par, volume 3149 of Lecture Notes in Computer Science, page 516-524. Springer, (2004)Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors., , , , , and . ACM Trans. Archit. Code Optim., 2 (3): 247-279 (2005)