Author of the publication

MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array.

, , , , , , , , , , and . ICECS, page 1-5. IEEE, (2023)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A Time-Domain Current-Mode MAC Engine for Analogue Neural Networks in Flexible Electronics., , , and . BioCAS, page 1-4. IEEE, (2019)SPICE Compact Modeling of Bipolar/Unipolar Memristor Switching Governed by Electrical Thresholds., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (8): 1255-1264 (2016)AnalogNets: ML-HW Co-Design of Noise-robust TinyML Models and Always-On Analog Compute-in-Memory Accelerator., , , , , , , , , and . CoRR, (2021)A Fokker-Planck Solver to Model MTJ Stochasticity., , and . ESSDERC, page 263-266. IEEE, (2021)MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array., , , , , , , , , and 1 other author(s). ICECS, page 1-5. IEEE, (2023)27.2 M0N0: A Performance-Regulated 0.8-to-38MHz DVFS ARM Cortex-M33 SIMD MCU with 10nW Sleep Power., , , , , , , , , and 1 other author(s). ISSCC, page 422-424. IEEE, (2020)Evolution of radiation-induced soft errors in FinFET SRAMs under process variations beyond 22nm., , and . NANOARCH, page 112-117. IEEE Computer Society, (2015)Training DNN IoT Applications for Deployment On Analog NVM Crossbars., , and . CoRR, (2019)ML-HW Co-Design of Noise-Robust TinyML Models and Always-On Analog Compute-in-Memory Edge Accelerator., , , , , , , , , and . IEEE Micro, 42 (6): 76-87 (2022)AR-PIM: An Adaptive-Range Processing-in-Memory Architecture., , , and . ISLPED, page 1-6. IEEE, (2023)