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Disambiguation of "Gielen, Georges G. E."

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Boosting Latent Defect Coverage in Automotive Mixed-Signal ICs Using SVM Classifiers.

, , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (10): 3426-3435 (October 2023)

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Georges Gielen

Marlis Gielen

Michael E G Kaes

Volker E G Beckmann

G E M Panhuysen

 

Other publications of authors with the same name

Modeling of the Power-supply Interactions of CMOS Operational Amplifiers Using Symbolic Computation., and . ISCAS, page 1381-1384. IEEE, (1993)Efficient simulation model for DAC dynamic properties., and . ISCAS, page 2896-2899. IEEE, (2010)A novel operating-point driven method for the sizing of analog IC., , , and . ISCAS, page 781-784. IEEE, (2011)Far-Field On-Chip Antennas Monolithically Integrated in a Wireless-Powered 5.8-GHz Downlink/UWB Uplink RFID Tag in 0.18-μm Standard CMOS., , , , , and . IEEE J. Solid State Circuits, 45 (9): 1746-1758 (2010)Degradation-Resilient Design of a Self-Healing xDSL Line Driver in 90 nm CMOS., and . IEEE J. Solid State Circuits, 47 (7): 1757-1767 (2012)A 42 fJ/Step-FoM Two-Step VCO-Based Delta-Sigma ADC in 40 nm CMOS., and . IEEE J. Solid State Circuits, 50 (3): 714-723 (2015)Guest editorial., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (2): 121-123 (2003)Digital ground bounce reduction by supply current shaping and clock frequency Modulation., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (1): 65-76 (2005)Behavioral modeling of (coupled) harmonic oscillators., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (8): 1017-1026 (2003)Globally Reliable Variation-Aware Sizing of Analog Integrated Circuits via Response Surfaces and Structural Homotopy., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 28 (11): 1627-1640 (2009)