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A Hardware Perspective on the ChaCha Ciphers: Scalable Chacha8/12/20 Implementations Ranging from 476 Slices to Bitrates of 175 Gbit/s.

, , , , and . SoCC, page 294-299. IEEE, (2019)

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Hardware architecture of an Internet Protocol Version 6 processor., , , and . SoCC, page 198-203. IEEE, (2014)Low-power high-speed on-chip asynchronous Wave-pipelined CML SerDes., , , and . SoCC, page 5-10. IEEE, (2014)A 2.5 GHz All-Digital Multiphase DLL and Phase Shifter in 65 nm CMOS using a Scalable Phase-to-Digital Converter., , and . ISCAS, page 1-5. IEEE, (2019)Low-Power All-Digital Multiphase DLL Design Using a Scalable Phase-to-Digital Converter., and . IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 67-I (4): 1158-1168 (2020)Real-time sleep detection and warning system to ensure driver's safety based on EEG., , , and . DDECS, page 231-236. IEEE, (2016)A 10 GbE TCP/IP hardware stack as part of a protocol acceleration platform., , , , , and . ICCE-Berlin, page 381-384. IEEE, (2013)The long way to power efficient, high performance DRAMs., and . PATMOS, page 289-290. IEEE, (2016)Robust design methodology for switched capacitor delta sigma modulators based on current conveyors., and . NEWCAS, page 277-280. IEEE, (2014)Low-power design of hybrid digital impedance calibration for process, voltage, temperature compensations., , , and . ICECS, page 37-40. IEEE, (2013)A Low-Power and Area-Efficient Digitally Controlled Shunt-Capacitor Delay Element for High-Resolution Delay Lines., and . ICECS, page 717-720. IEEE, (2018)