( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Zero aliasing compression.

, , и . FTCS, стр. 254-263. IEEE Computer Society, (1990)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Prakash Pradhan

Merina Pradhan

Swapna Pradhan

Anup Pradhan

Amir Man Pradhan

 

Другие публикации лиц с тем же именем

Processor- and Memory-Based Checkpoint and Rollback Recovery., и . Computer, 26 (2): 22-31 (1993)VERILAT: verification using logic augmentation and transformations., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (9): 1041-1051 (2000)GfXpress: A Technique for Synthesis and Optimization of GF(2m) Polynomials., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (4): 698-711 (2008)Processor Allocation in Hypercube Multicomputers: Fast and Efficient Strategies for Cubic and Noncubic Allocation., и . IEEE Trans. Parallel Distributed Syst., 6 (10): 1108-1122 (1995)Simplified bit parallel systolic multipliers for special class of galois field (2m) with testability., , , и . IET Comput. Digit. Tech., 4 (5): 428-437 (2010)On the Design and Optimization of a Quantum Polynomial-Time Attack on Elliptic Curve Cryptography., , , и . TQC, том 5106 из Lecture Notes in Computer Science, стр. 96-104. Springer, (2008)Roll-Forward Checkpointing Schemes., , и . Hardware and Software Architectures for Fault Tolerance, том 774 из Lecture Notes in Computer Science, стр. 95-116. Springer, (1993)ULS: A dual-Vth/high-kappa nano-CMOS universal level shifter for system-level power management., и . JETC, 6 (2): 8:1-8:26 (2010)RTRAM: Reconfigurable and Testable Multi-Bit RAM Design., и . ITC, стр. 263-278. IEEE Computer Society, (1988)NiVER: Non Increasing Variable Elimination Resolution for Preprocessing SAT instances., и . SAT, (2004)