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Machine Learning on the Thermal Side-Channel: Analysis of Accelerator-Rich Architectures.

, , , and . ICCD, page 83-91. IEEE Computer Society, (2018)

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Time Domain Sequential Locking for Increased Security., and . ISCAS, page 1-5. IEEE, (2018)A framework for exploring alternative fault-tolerant schemes targeting 3-D reconfigurable architectures., , and . SAMOS, page 336-341. IEEE, (2016)Protecting analog circuits with parameter biasing obfuscation., and . LATS, page 1-6. IEEE, (2017)Power conversion efficiency-aware mapping of multithreaded applications on heterogeneous architectures: A comprehensive parameter tuning., , , and . ASP-DAC, page 70-75. IEEE, (2018)Multi-Voltage Domain Power Distribution Network for Optimized Ultra-Low Voltage Clock Delivery., and . IGSC, page 1-8. IEEE, (2018)Clock distribution networks for 3-D ictegrated Circuits., , and . CICC, page 651-654. IEEE, (2008)ElasticCore: A Dynamic Heterogeneous Platform With Joint Core and Voltage/Frequency Scaling., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (2): 249-261 (2018)Editorial., , , , , , , , , and 35 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 25 (1): 1-20 (2017)Increased Output Corruption and Structural Attack Resilience for SAT Attack Secure Logic Locking., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (1): 38-51 (2021)Synthesis of Coupling Capacitance Based Hidden State Transitions for Sequential Logic Locking., and . ISCAS, page 1734-1738. IEEE, (2022)