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Machine Learning on the Thermal Side-Channel: Analysis of Accelerator-Rich Architectures.

, , , and . ICCD, page 83-91. IEEE Computer Society, (2018)

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Time Domain Sequential Locking for Increased Security., and . ISCAS, page 1-5. IEEE, (2018)Increased Output Corruption and Structural Attack Resilience for SAT Attack Secure Logic Locking., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (1): 38-51 (2021)Hidden Costs of Analog Deobfuscation Attacks., , and . IEEE Trans. Very Large Scale Integr. Syst., 31 (11): 1802-1815 (November 2023)Deep Learning Sparse Array Design Using Binary Switching Configurations., , , and . ICASSP, page 1-5. IEEE, (2023)Characterization of In-Cone Logic Locking Resiliency Against the SAT Attack., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (8): 1607-1620 (2020)Lightweight Hardware Implementation of Binary Ring-LWE PQC Accelerator., , , , , , , , , and . IEEE Comput. Archit. Lett., 21 (1): 17-20 (2022)Physical Layer Encryption for Wireless OFDM Communication Systems., , , , and . J. Hardw. Syst. Secur., 4 (3): 230-245 (2020)Importance of Multi-parameter SAT Attack Exploration for Integrated Circuit Security., and . APCCAS, page 366-369. IEEE, (2018)Increasing the SAT Attack Resiliency of In-Cone Logic Locking., and . ISCAS, page 1-5. IEEE, (2019)Security Vulnerabilities of Obfuscated Analog Circuits., , and . ISCAS, page 1-5. IEEE, (2020)