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ATPG for Design Errors-Is It Possible?, , , , and . VTS, page 283-285. IEEE Computer Society, (2001)A Fast Signature Simulation Tool for Built-In Self-Testing Circuits., , , , and . DAC, page 17-25. IEEE Computer Society Press / ACM, (1987)Test Compaction in a Parallel Access Scan Environment., and . Asian Test Symposium, page 300-305. IEEE Computer Society, (1997)Current and Future Directions in Automatic Test Pattern Generation for Power Delivery Network Validation.. Asian Test Symposium, page 233-238. IEEE Computer Society, (2012)Test Cycle Count Reduction in a Parallel Scan BIST Environment., and . J. Electron. Test., 16 (5): 409-418 (2000)The economics of scan-path design for testability., and . J. Electron. Test., 5 (2-3): 179-193 (1994)An Analysis of the Economics of Self Test., , and . ITC, page 20-30. IEEE Computer Society, (1984)System chip test: are we there yet?. ITC, page 1144. IEEE Computer Society, (1998)A Unifying Methodology for Intellectual Property and Custom Logic Testing., , and . ITC, page 639-648. IEEE Computer Society, (1996)Delay Fault Testing: How Robust are Our Models?, , , , and . VTS, page 502-503. IEEE Computer Society, (1996)