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Boolean Functions Classification via Fixed Polarity Reed-Muller Forms., and . IEEE Trans. Computers, 46 (2): 173-186 (1997)Delay and Area Optimization in Standard-Cell Design., , and . DAC, page 349-352. IEEE Computer Society Press, (1990)Clock network sizing via sequential linear programming with time-domain analysis., and . ISPD, page 182-189. ACM, (2004)System-Level Floorplan-Aware Analysis of Integrated CPU-GPUs., and . DAC, page 137:1-137:6. ACM, (2014)Pre-layout wire length and congestion estimation., and . DAC, page 582-587. ACM, (2004)Buffer sizing for clock power minimization subject to general skew constraints., and . DAC, page 159-164. ACM, (2004)Aggressor alignment for worst-case crosstalk noise., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20 (5): 612-621 (2001)The crossing distribution problem IC layout., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 14 (4): 423-433 (1995)A new reasoning scheme for efficient redundancy addition and removal., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (7): 945-951 (2003)Eliminating false positives in crosstalk noise analysis., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (9): 1406-1419 (2005)