( en | de | ru )

 

Disambiguation of "Zaruba, Florian"

Author of the publication

copydeleteadd this publication to your clipboard
Reducing Load-Use Dependency-Induced Performance Penalty in the Open-Source RISC-V CVA6 CPU.

, , , and . DSD, page 429-435. IEEE, (2023)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Hans Zaruba

Marc-Michael Zaruba

Florian Klasovsky

Syntheseparameter-Reaktivitätsbeziehungen für neue Palladiumoxidkatalysatoren in feinchemischen Hydrierungen. TU Darmstadt, (2009)

Florian Franz

Realzeittest von Fahrzeugsoftware-Komponenten. TU München, (2009)

Florian Beißner

Funktionelle Bildgebung des vegetativen Nervensystems: neue Ansätze zur fMRT-Messung des menschlichen Hirnstamms. Uni Frankfurt Main, (2010)
 

Other publications of authors with the same name

Stream Semantic Registers: A Lightweight RISC-V ISA Extension Achieving Full Compute Utilization in Single-Issue Cores., , , and . IEEE Trans. Computers, 70 (2): 212-227 (2021)FPnew: An Open-Source Multi-Format Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing., , , and . CoRR, (2020)A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing., , and . Hot Chips Symposium, page 1-24. IEEE, (2020)Ara: A 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOI., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (2): 530-543 (2020)Ara: A 1 GHz+ Scalable and Energy-Efficient RISC-V Vector Processor with Multi-Precision Floating Point Support in 22 nm FD-SOI., , , , and . CoRR, (2019)Tiny-FPU: Low-Cost Floating-Point Support for Small RISC-V MCU Cores., , , , , and . ISCAS, page 1-5. IEEE, (2021)Manticore: A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing., , and . CoRR, (2020)A 0.80pJ/flop, 1.24Tflop/sW 8-to-64 bit Transprecision Floating-Point Unit for a 64 bit RISC-V Processor in 22nm FD-SOI., , , and . VLSI-SoC, page 95-98. IEEE, (2019)The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-Ready 1.7-GHz 64-Bit RISC-V Core in 22-nm FDSOI Technology., and . IEEE Trans. Very Large Scale Integr. Syst., 27 (11): 2629-2640 (2019)FPnew: An Open-Source Multiformat Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing., , , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (4): 774-787 (2021)