( en | de | ru )

 

Disambiguation of "Afzali-Kusha, Ali"

Author of the publication

copydeleteadd this publication to your clipboard
Toward Approximate Computing for Coarse-Grained Reconfigurable Architectures.

, , , , and . IEEE Micro, 38 (6): 63-72 (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Dariush Afzali

Wien Kusharyoto

Jörg Kushauer

ali

Ali Aassie Ali

 

Other publications of authors with the same name

All-Region Statistical Model for Delay Variation Based on Log-Skew-Normal Distribution., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (9): 1503-1508 (2016)OPLE: A Heuristic Custom Instruction Selection Algorithm Based on Partitioning and Local Exploration of Application Dataflow Graphs., , , and . ACM Trans. Embed. Comput. Syst., 14 (4): 72:1-72:23 (2015)Sign bit reduction encoding for low power applications., , and . DAC, page 214-217. ACM, (2005)BZ-FAD: A Low-Power Low-Area Multiplier Based on Shift-and-Add Architecture., , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (2): 302-306 (2009)Scan-Based Structure with Reduced Static and Dynamic Power Consumption., , , , and . J. Low Power Electron., 2 (3): 477-487 (2006)A Theoretical Framework for Quality Estimation and Optimization of DSP Applications Using Low-Power Approximate Adders., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (1): 327-340 (2019)Systematic test program generation for SoC testing using embedded processor., , , and . ISCAS (5), page 541-544. IEEE, (2003)High performance circuit techniques for dynamic OR gates., , and . ISCAS, IEEE, (2006)WL-VC SRAM: a low leakage memory circuit for deep sub-micron design., , and . ISCAS, IEEE, (2006)An Efficient Clocking Scheme for On-Chip Communications., , , and . APCCAS, page 119-122. IEEE, (2006)