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Formal Verification in the Loop to Enhance Verification of Safety-Critical Cyber-physical Systems.

, , and . ECEASST, (2019)

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Checking secure information flow in Java bytecode by code transformation and standard bytecode verification., , , and . Softw. Pract. Exp., 34 (13): 1225-1255 (2004)ASSESS: A Simulator of Soft Errors in the Configuration Memory of SRAM-Based FPGAs., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 33 (9): 1342-1355 (2014)Formal approaches to SEU testing in FPGAs., , and . AHS, page 209-216. IEEE, (2013)Towards a Formalization of System Requirements for an Integrated Clinical Environment., , and . EAI Endorsed Trans. Self Adapt. Syst., 2 (6): e3 (2016)A framework for FMI-based co-simulation of human-machine interfaces., , and . Softw. Syst. Model., 19 (3): 601-623 (2020)Formally Verifying Fault Tolerant System Designs., , and . Comput. J., 43 (3): 191-205 (2000)Towards Stochastic FMI Co-Simulations: Implementation of an FMU for a Stochastic Activity Networks Simulator., , and . STAF Workshops, volume 11176 of Lecture Notes in Computer Science, page 34-44. Springer, (2018)SEU-X: A SEu un-excitability prover for SRAM-FPGAs., , and . IOLTS, page 25-30. IEEE Computer Society, (2012)Modeling and generation of secure component communications in AUTOSAR., , , and . SAC, page 1473-1480. ACM, (2017)Co-simulation and Verification of a Non-linear Control System for Cogging Torque Reduction in Brushless Motors., , , and . SEFM Workshops, volume 12226 of Lecture Notes in Computer Science, page 3-19. Springer, (2019)