Author of the publication

Hierarchical Loop Partitioning for Rapid Generation of Runtime Configurations.

, , , , and . ARC, volume 5992 of Lecture Notes in Computer Science, page 282-293. Springer, (2010)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Preprocessing technique for accelerating reconfiguration of degradable VLSI arrays., , , and . ISCAS, page 2424-2427. IEEE, (2013)Low-complexity pruning for accelerating corner detection., , , and . ISCAS, page 1684-1687. IEEE, (2012)Instruction set customization for area-constrained FPGA designs., , , and . SoCC, page 329-334. IEEE, (2011)Dynamically Growing Neural Network Architecture for Lifelong Deep Learning on the Edge., , , , and . FPL, page 262-268. IEEE, (2020)A Lightweight Detection Algorithm For Collision-Optimized Divide-and-Conquer Attacks., , , , and . IEEE Trans. Computers, 69 (11): 1694-1706 (2020)Improving accuracy of HPC-based malware classification for embedded platforms using gradient descent optimization., , , , and . J. Cryptogr. Eng., 10 (4): 289-303 (2020)A Unified Multi-Task Learning Architecture for Fast and Accurate Pedestrian Detection., , and . IEEE Trans. Intell. Transp. Syst., 23 (2): 982-996 (2022)Selecting profitable custom instructions for reconfigurable processors., , , , and . J. Syst. Archit., 56 (8): 340-351 (2010)FPGA-aware techniques for rapid generation of profitable custom instructions., , , and . Microprocess. Microsystems, 37 (3): 259-269 (2013)Travel-Time Prediction of Bus Journey With Multiple Bus Trips., , , and . IEEE Trans. Intell. Transp. Syst., 20 (11): 4192-4205 (2019)