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Application-level Validation of Accelerator Designs Using a Formal Software/Hardware Interface., , , , , , , , , and 3 other author(s). ACM Trans. Design Autom. Electr. Syst., 29 (2): 35:1-35:25 (March 2024)AutoSoC: Automating Algorithm-SOC Co-design for Aerial Robots., , , and . CoRR, (2021)SM6: A 16nm System-on-Chip for Accurate and Noise-Robust Attention-Based NLP Applications : The 33rd Hot Chips Symposium - August 22-24, 2021., , , , , , , , , and . HCS, page 1-13. IEEE, (2021)GoldenEye: A Platform for Evaluating Emerging Numerical Data Formats in DNN Accelerators., , , , and . DSN, page 206-214. IEEE, (2022)EdgeBERT: Optimizing On-Chip Inference for Multi-Task NLP., , , , , , , , and . CoRR, (2020)A 16-nm SoC for Noise-Robust Speech and NLP Edge AI Inference With Bayesian Sound Source Separation and Attention-Based DNNs., , , , , , , , , and . IEEE J. Solid State Circuits, 58 (2): 569-581 (February 2023)VaPr: Variable-Precision Tensors to Accelerate Robot Motion Planning., , , , , , , and . IROS, page 6304-6309. (2023)14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration., , , , , , , , , and 19 other author(s). ISSCC, page 262-264. IEEE, (2024)MASR: A Modular Accelerator for Sparse RNNs., , , , , , , and . PACT, page 1-14. IEEE, (2019)Algorithm-Hardware Co-Design of Adaptive Floating-Point Encodings for Resilient Deep Learning Inference., , , , , , , and . DAC, page 1-6. IEEE, (2020)