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TaPEr: tackling power emergencies in the dark silicon era by exploiting resource scalability., , and . Conf. Computing Frontiers, page 16:1-16:8. ACM, (2015)Compilation for Distributed Memory Architectures., and . The Compiler Design Handbook, CRC Press, (2002)Reducing Energy Consumption in Chip Multiprocessors Using Workload Variations., , , , and . Ultra Low-Power Electronics and Design, Kluwer / Springer, (2004)Soft errors issues in low-power caches., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (10): 1157-1166 (2005)Selective Caching: Avoiding Performance Valleys in Massively Parallel Architectures., , and . PDP, page 290-298. IEEE, (2020)Optimising power efficiency in trace cache fetch unit., , , and . IET Comput. Digit. Tech., 1 (4): 334-348 (2007)Multiverse: Dynamic VM Provisioning for Virtualized High Performance Computing Clusters., , , , , and . CCGRID, page 131-141. IEEE, (2020)A Constraint Network Based Approach to Memory Layout Optimization, , and . CoRR, (2007)Thermal-Aware Task Allocation and Scheduling for Embedded Systems, , , , and . CoRR, (2007)Hybrid-comp: A criticality-aware compressed last-level cache., , , and . ISQED, page 25-30. IEEE, (2018)