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Design and implication of a rule based weight sparsity module in HTM spatial pooler., , and . ICECS, page 274-277. IEEE, (2017)On-chip Face Recognition System Design with Memristive Hierarchical Temporal Memory., , , , and . CoRR, (2017)Memristive Operational Amplifiers., , , and . BICA, volume 41 of Procedia Computer Science, page 114-119. Elsevier, (2014)Hierarchical Temporal Memory Features with Memristor Logic Circuits for Pattern Recognition., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (6): 1143-1156 (2018)A design of HTM spatial pooler for face recognition using memristor-CMOS hybrid circuits., , , and . ISCAS, page 1254-1257. IEEE, (2016)Towards Two-Stream Foveation-based Active Vision Learning., , , and . CoRR, (2024)Exploring Foveation and Saccade for Improved Weakly-Supervised Localization., , , and . Gaze Meets ML, volume 226 of Proceedings of Machine Learning Research, page 61-89. PMLR, (2023)On-chip face recognition system design with memristive Hierarchical Temporal Memory., , , , and . J. Intell. Fuzzy Syst., 34 (3): 1393-1402 (2018)TraNNsformer: Clustered Pruning on Crossbar-Based Architectures for Energy-Efficient Neural Networks., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (10): 2361-2374 (2020)HTM Spatial Pooler With Memristor Crossbar Circuits for Sparse Biometric Recognition., , , and . IEEE Trans. Biomed. Circuits Syst., 11 (3): 640-651 (2017)