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TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP.

, , , , , , , , , и . ACM Trans. Archit. Code Optim., 1 (1): 62-93 (2004)

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Scott McDonald

Robert G Claassen

Robert G Eisenhauer

Robert G Perneczky

Robert G Lebrecht

 

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Scaling to the End of Silicon with EDGE Architectures., , , , , , , , , и . Computer, 37 (7): 44-55 (2004)Organization and implementation of the register-renaming mapper for out-of-order IBM POWER4 processors., , , , , , и . IBM J. Res. Dev., 49 (1): 167-188 (2005)Design and Implementation of the TRIPS Primary Memory System., , , , и . ICCD, стр. 470-476. IEEE, (2006)Implementation and Evaluation of On-Chip Network Architectures., , , , и . ICCD, стр. 477-484. IEEE, (2006)Implementation and Evaluation of a Dynamically Routed Processor Operand Network., , , , , , и . NOCS, стр. 7-17. IEEE Computer Society, (2007)Dataflow Predication., , , , , , и . MICRO, стр. 89-102. IEEE Computer Society, (2006)Distributed Microarchitectural Protocols in the TRIPS Prototype Processor., , , , , , , , , и 7 other автор(ы). MICRO, стр. 480-491. IEEE Computer Society, (2006)Critical path analysis of the TRIPS architecture., , , , и . ISPASS, стр. 37-47. IEEE Computer Society, (2006)TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP., , , , , , , , , и . ACM Trans. Archit. Code Optim., 1 (1): 62-93 (2004)