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Larrabee: A Many-Core x86 Architecture for Visual Computing., , , , , , , , , and 4 other author(s). IEEE Micro, 29 (1): 10-21 (2009)Issues in the implementation of the i486TM cache and bus., and . ICCD, page 193-198. IEEE, (1989)Improving the energy efficiency of Big Cores., , , , , , and . ISCA, page 493-504. IEEE Computer Society, (2014)Best of Both Latency and Throughput., , , and . ICCD, page 236-243. IEEE Computer Society, (2004)Performance Benefits of Heterogeneous Computing in HPC Workloads., , and . IPDPS Workshops, page 16-26. IEEE Computer Society, (2012)Microarchitectural Simulation and Control of di/dt-induced Power Supply Voltage Variation., , and . HPCA, page 7-16. IEEE Computer Society, (2002)Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation., , , , , and . HPCA, page 187-196. IEEE Computer Society, (2002)Implications of Device Timing Variability on Full Chip Timing., , and . HPCA, page 37-45. IEEE Computer Society, (2007)Larrabee: a many-core x86 architecture for visual computing., , , , , , , , , and 4 other author(s). ACM Trans. Graph., 27 (3): 18 (2008)Microarchitectural dI/dt Control., , and . IEEE Des. Test Comput., 20 (3): 40-47 (2003)