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Datapath fault tolerance for parallel accelerators., and . FPT, page 366-369. IEEE, (2013)KAPow: High-Accuracy, Low-Overhead Online Per-Module Power Estimation for FPGA Designs., , , , , and . ACM Trans. Reconfigurable Technol. Syst., 11 (1): 2:1-2:22 (2018)KOCL: Power Self- Awareness for Arbitrary FPGA-SoC-Accelerated OpenCL Applications., , , , , and . IEEE Des. Test, 34 (6): 36-45 (2017)LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference., , , and . CoRR, (2019)Achieving low-overhead fault tolerance for parallel accelerators with dynamic partial reconfiguration., and . FPL, page 1-6. IEEE, (2014)Logic Shrinkage: Learned Connectivity Sparsification for LUT-Based Neural Networks., , , , , , and . ACM Trans. Reconfigurable Technol. Syst., 16 (4): 57:1-57:25 (December 2023)Digit Stability Inference for Iterative Methods Using Redundant Number Representation., , , and . IEEE Trans. Computers, 70 (7): 1074-1080 (2021)ARCHITECT: Arbitrary-precision Hardware with Digit Elision for Efficient Iterative Compute., , , and . CoRR, (2019)Predicting antimicrobial resistance using conserved genes., , , , and . PLoS Comput. Biol., (2020)KOCL: Kernel-level Power Estimation for Arbitrary FPGA-SoC-accelerated OpenCL Applications., , , , , and . IWOCL, page 4:1. ACM, (2018)