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Digital Analog Design: Enabling Mixed-Signal System Validation., , , , and . IEEE Des. Test, 32 (1): 44-52 (2015)On-Chip Measurement of Jitter Transfer and Supply Sensitivity of PLL/DLLs.. IEEE Trans. Circuits Syst. II Express Briefs, 56-II (6): 449-453 (2009)Adaptive-Bandwidth Phase-Locked Loop With Continuous Background Frequency Calibration.. IEEE Trans. Circuits Syst. II Express Briefs, 56-II (3): 205-209 (2009)Simulation and Analysis of Random Decision Errors in Clocked Comparators., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (8): 1844-1857 (2009)Accurate and Efficient CPU/GPU-Based 3-DOF Haptic Rendering of Complex Static Virtual Environments., , , , and . Presence Teleoperators Virtual Environ., 18 (5): 340-360 (2009)Probabilistic Bug Localization via Statistical Inference based on Partially Observed Data., , and . DAC, page 120:1-120:6. ACM, (2014)Equalizer design and performance trade-offs in ADC-based serial links., , , , , and . CICC, page 1-8. IEEE, (2010)Event-driven simulation of Volterra series models in SystemVerilog., , and . CICC, page 1-4. IEEE, (2013)Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL., , , , and . IEEE J. Solid State Circuits, 38 (11): 1795-1803 (2003)A 1.2-V-only 900-mW 10 gb ethernet transceiver and XAUI interface with robust VCO tuning technique., , , , , , , , and . IEEE J. Solid State Circuits, 40 (11): 2148-2158 (2005)