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Scalable 0.35 V to 1.2 V SRAM Bitcell Design From 65 nm CMOS to 28 nm FDSOI., , , , , , , , and . IEEE J. Solid State Circuits, 49 (7): 1499-1505 (2014)Working with Lowell.. AKCE Int. J. Graphs Comb., 17 (2): 641-645 (2020)A 6-Wire Plug and Play Clockless Distributed On-Chip-Sensor Network in 28 nm UTBB FD-SOI., , , and . J. Low Power Electron., 14 (3): 404-413 (2018)Logical effort model extension to propagation delay representation., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (9): 1677-1684 (2006)The impact of different slot design of BLDC motor in a complete drive system., , , and . IECON, page 4300-4305. IEEE, (2020)27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking., , , , , , , , , and 12 other author(s). ISSCC, page 452-453. IEEE, (2014)Yield Enhancement Methodology for CMOS Standard Cells., , , , , , , and . ISQED, page 497-502. IEEE Computer Society, (2006)A fine grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32nm GALS MPSoC., , , , , , , , , and 3 other author(s). ESSCIRC, page 57-60. IEEE, (2013)Effect of Varying Number of Poles on Performance of a PM-Assisted Synchronous Reluctance Machine Enabled with Iron Nitride Magnet Combinations., , and . IECON, page 1-6. IEEE, (2023)Product On-Chip Process Compensation for Low Power and Yield Enhancement., , , , , , , , , and 3 other author(s). PATMOS, volume 5953 of Lecture Notes in Computer Science, page 247-255. Springer, (2009)