( en | de | ru )

 

Disambiguation of "Saxena, Utkarsh"

Author of the publication

copydeleteadd this publication to your clipboard
HCiM: ADC-Less Hybrid Analog-Digital Compute in Memory Accelerator for Deep Learning Workloads.

, , , and . CoRR, (2024)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Utkarsh Jain

Abhinav Saxena

Ambrish Saxena

Sabine Saxena

Amit Saxena

 

Other publications of authors with the same name

Revisiting Stochastic Computing in the Era of Nanoscale Nonvolatile Technologies., , , , , , , , , and 1 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 28 (12): 2481-2494 (2020)On-chip learning for domain wall synapse based Fully Connected Neural Network., , , , , and . CoRR, (2018)Augmenting smart home network security using blockchain technology., , and . Int. J. Electron. Secur. Digit. Forensics, 12 (1): 99-117 (2020)McQueen: Mixed Precision Quantization of Early Exit Networks., and . BMVC, page 511-513. BMVA Press, (2023)Compute-in-Memory Technologies and Architectures for Deep Learning Workloads., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 30 (11): 1615-1630 (2022)Hardware/Software co-design with ADC-Less In-memory Computing Hardware for Spiking Neural Networks., , , and . CoRR, (2022)Embracing Stochasticity to Enable Neuromorphic Computing at the Edge., , , and . IEEE Des. Test, 38 (6): 28-35 (2021)Prediction of Syncope based on Physiological Data Analysis using Decision Tree Algorithm., , and . ICCE-TW, page 1-2. IEEE, (2020)Towards ADC-Less Compute-In-Memory Accelerators for Energy Efficient Deep Learning., , and . DATE, page 624-627. IEEE, (2022)Hardware/Software Co-Design With ADC-Less In-Memory Computing Hardware for Spiking Neural Networks., , , and . IEEE Trans. Emerg. Top. Comput., 12 (1): 35-47 (January 2024)