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Disambiguation of "Jr., Earl E. Swartzlander"

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Implementation of a Single Chip, Pipelined, Complex, One-Dimensional Fast FourierTransform in 0.25 mu m BulkCMOS.

, , , , and . ASAP, page 335-343. IEEE Computer Society, (2002)

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Other publications of authors with the same name

A Spanning Tree Carry Lookahead Adder., and . IEEE Trans. Computers, 41 (8): 931-939 (1992)A systolic array for 2-D DFT and 2-D DCT., and . ASAP, page 123-131. IEEE, (1994)Parallel Counters.. IEEE Trans. Computers, 22 (11): 1021-1024 (1973)The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm., , and . VLSI-SoC (Selected Papers), volume 291 of IFIP, page 1-22. Springer, (2007)Dadda Multiplier designs using memristors., and . ICICDT, page 1-4. IEEE, (2017)Quantifying academic placer performance on custom designs., , , , , and . ISPD, page 91-98. ACM, (2011)The Sign/Logarithm Number System., and . IEEE Trans. Computers, 24 (12): 1238-1242 (1975)Calculators.. IEEE Ann. Hist. Comput., 20 (1): 67-76 (1998)Calculators.. IEEE Ann. Hist. Comput., 17 (3): 75-77 (1995)A Variable-Latency Architecture for Accelerating Deterministic Approaches to Stochastic Computing., and . ACSSC, page 608-613. IEEE, (2019)