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Design and analysis of semaphore precedence constraints: A model-based approach for deterministic communications.

, , , , , and . DATE, page 231-236. IEEE, (2018)

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Quality of Fault Injection Strategies on Hardware Accelerator., , , , and . SAFECOMP, volume 13414 of Lecture Notes in Computer Science, page 222-236. Springer, (2022)Design and analysis of semaphore precedence constraints: A model-based approach for deterministic communications., , , , , and . DATE, page 231-236. IEEE, (2018)Guest editorial: special issue on Real-Time and Network Systems., and . Real Time Syst., 55 (2): 293-295 (2019)Verification for Object Detection - IBP IoU., , , , , , and . CoRR, (2024)GRec: Automatic Computation of Reconfiguration Graphs for Multi-core Platforms., and . ACM Trans. Embed. Comput. Syst., 18 (5): 41:1-41:24 (2019)On How to Identify Cache Coherence: Case of the NXP QorIQ T4240., , and . ECRTS, volume 165 of LIPIcs, page 13:1-13:22. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, (2020)Identification of Multi-Core Interference., , and . HASE, page 98-106. IEEE, (2019)Modeling Cache Coherence to Expose Interference (Artifact)., , and . Dagstuhl Artifacts Ser., 5 (1): 07:1-07:2 (2019)ACETONE: Predictable Programming Framework for ML Applications in Safety-Critical Systems (Artifact)., , , and . Dagstuhl Artifacts Ser., 8 (1): 06:1-06:2 (2022)Safety Verification of Neural Network Controlled Systems., , , and . DSN Workshops, page 47-54. IEEE, (2021)