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Low-power processor architecture exploration for online biomedical signal analysis.

, , , , and . IET Circuits Devices Syst., 6 (5): 279-286 (2012)

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Low-power processor architecture exploration for online biomedical signal analysis., , , , and . IET Circuits Devices Syst., 6 (5): 279-286 (2012)Sub-Word Parallel Precision-Scalable MAC Engines for Efficient Embedded DNN Inference., , , , , , and . AICAS, page 6-10. IEEE, (2019)TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing., , , , , , and . VLSI-SoC, page 159-164. IEEE, (2012)Investigating the Potential of Custom Instruction Set Extensions for SHA-3 Candidates on a 16-bit Microcontroller Architecture., , and . IACR Cryptology ePrint Archive, (2012)Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment., , , , and . DATE, page 381-386. ACM, (2015)A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI., , , and . ISCAS, page 1-4. IEEE, (2018)Synchronizing code execution on ultra-low-power embedded multi-channel signal analysis platforms., , , , , and . DATE, page 396-399. EDA Consortium San Jose, CA, USA / ACM DL, (2013)An FPGA-Based 4 Mbps Secret Key Distillation Engine for Quantum Key Distribution Systems., , , , , , and . J. Signal Process. Syst., 86 (1): 1-15 (2017)Statistical fault injection for impact-evaluation of timing errors on application performance., , , , and . DAC, page 13:1-13:6. ACM, (2016)DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment., , , , , and . ESSCIRC, page 261-264. IEEE, (2016)