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Disambiguation of "Loi, Igor"

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Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal Processing.

, , , , and . PATMOS, volume 6951 of Lecture Notes in Computer Science, page 102-111. Springer, (2011)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Hugo Loi

Simona Loi

Salvatore Loiero

Fundamentalmetanoia: Untersuchungen zu einem Ort eschato-praktischer Erfahrungs- und Erinnerungskultur. Uni Tübingen, habilitation, (2009)

Phuc-Loi Luu

Tran Loi Chung

 

Other publications of authors with the same name

Area and Power Modeling for Networks-on-Chip with Layout Awareness., , , , , , and . VLSI Design, (2007)A shared-FPU architecture for ultra-low power MPSoCs., , and . Conf. Computing Frontiers, page 3:1-3:8. ACM, (2013)Configurable Low-Latency Interconnect for Multi-core Clusters., , , , and . VLSI-SoC (Selected Papers), volume 418 of IFIP Advances in Information and Communication Technology, page 107-124. Springer, (2012)Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode., , , , , , , , , and 2 other author(s). CoRR, (2021)A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors., , , , , , , and . IEEE Des. Test, 34 (6): 46-53 (2017)Variation-Tolerant Architecture for Ultra Low Power Shared-L1 Processor Clusters., , and . IEEE Trans. Circuits Syst. II Express Briefs, 59-II (12): 927-931 (2012)Synthesis of low-overhead configurable source routing tables for network interfaces., , and . DATE, page 262-267. IEEE, (2009)A resilient architecture for low latency communication in shared-L1 processor clusters., , and . DATE, page 887-892. IEEE, (2012)Energy-Efficient Two-level Instruction Cache Design for an Ultra-Low-Power Multi-core Cluster., , , and . DATE, page 1734-1739. IEEE, (2020)4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode., , , , , , , , , and 2 other author(s). ISSCC, page 60-62. IEEE, (2021)