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SWEC: a Step Wise Equivalent Conductance timing simulator for CMOS VLSI circuits., , and . EURO-DAC, page 142-148. EEE Computer Society, (1991)A new performance-driven global routing algorithm for gate array., , and . VLSI, volume A-42 of IFIP Transactions, page 321-330. North-Holland, (1993)Performance-Driven Steiner Tree Algorithm for Global Routing., , , , and . DAC, page 177-181. ACM Press, (1993)Recent advances in VLSI layout., and . Proc. IEEE, 78 (2): 237-263 (1990)Basic Circuit Theory, and . Tate McGrawHill, New Delhi, (2010)A Dynamic and Efficient Representation of Building-Block Layout., , and . DAC, page 376-384. IEEE Computer Society Press / ACM, (1987)Accurate reduced RL model for frequency dependent transmission lines., and . ICECS, page 761-764. IEEE, (2002)Post global routing crosstalk synthesis., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (12): 1418-1430 (1997)TIGER: an efficient timing-driven global router for gate array and standard cell layout design., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (11): 1323-1331 (1997)Routing Region Definition and Ordering Scheme for Building-Block Layout., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 4 (3): 189-197 (1985)