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A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platforms.

, , , , , , and . DAC, page 549-554. ACM, (2010)

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Control flow optimization for fast system simulation and storage minimization., , , , and . EDAC-ETC-EUROASIC, page 20-24. IEEE Computer Society, (1994)Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks., , , , , , , , , and 3 other author(s). DATE, page 103-108. IEEE, (2018)Energy efficient FFT implementation through stage skipping and merging., , and . CODES+ISSS, page 153-162. IEEE, (2015)Fast prototyping and refinement of complex dynamic data types in multimedia applications for consumer embedded devices., , , , , , and . ICME, page 803-806. IEEE Computer Society, (2004)System scenario framework evaluation on EFM32 using the H264/AVC encoder control structure., , and . ECCTD, page 1-4. IEEE, (2015)Run-time Task Overlapping on Multiprocessor Platforms., and . J. Signal Process. Syst., 60 (2): 169-182 (2010)Background memory area estimation for multidimensional signal processing systems., , and . IEEE Trans. Very Large Scale Integr. Syst., 3 (2): 157-172 (1995)Design and Synthesis of Pareto Buffers Offering Large Range Runtime Energy/Delay Tradeoffs Via Combined Buffer Size and Supply Voltage Tuning., , , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (1): 117-127 (2009)Parametric and Functional Degradation Analysis of Complete 14-nm FinFET SRAM., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (6): 1308-1321 (2019)Formalized three-layer system-level model and reuse methodology for embedded data-dominated applications., , , and . IEEE Trans. Very Large Scale Integr. Syst., 8 (2): 207-216 (2000)