( en | de | ru )

 

Disambiguation of "Martina, Maurizio"

Author of the publication

copydeleteadd this publication to your clipboard
HW-Flow: A Multi-Abstraction Level HW-CNN Codesign Pruning Methodology.

, , , , , , , , , and . Leibniz Trans. Embed. Syst., 8 (1): 03:1-03:30 (2022)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Maurizio Podda

Maurizio Venturini

Maurizio Zanazzi

Maurizio Podda

Maurizio Solinas

 

Other publications of authors with the same name

A Low Cost ALS and VLC Circuit for Solid State Lighting., and . ApplePies, page 461-467. Springer, (2018)Comparative Study of Keccak SHA-3 Implementations., , and . Cryptogr., 7 (4): 60 (September 2023)A power-scalable motion estimation coprocessor for energy constrained applications., , , and . ISSPA (2), page 603-604. IEEE, (2003)0-7803-7946-2.An Area-Efficient Variable-Size Fixed-Point DCT Architecture for HEVC Encoding., , and . IEEE Trans. Circuits Syst. Video Techn., 30 (1): 232-242 (2020)Efficient Hardware Implementation of the LEDAcrypt Decoder., , , , , and . IEEE Access, (2021)Vlsi Implementation of WiMAX Convolutional Turbo Code Encoder and Decoder., , and . J. Circuits Syst. Comput., 18 (3): 535-564 (2009)An LDPC Decoder Architecture for Wireless Sensor Network Applications., , and . Sensors, 12 (2): 1529-1543 (2012)Turbo NOC: a framework for the design of Network On Chip based turbo decoder architectures, and . CoRR, (2009)Novel JPEG 2000 Compliant DWT and IWT VLSI Implementations., , , and . VLSI Signal Processing, 35 (2): 137-153 (2003)TinyCL: An Efficient Hardware Architecture for Continual Learning on Autonomous Systems., , , , and . CoRR, (2024)