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A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck.

, , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 14 (3): 279-291 (2006)

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Trading Fault-Masking with Performance Overhead for FPGAs., and . ARCS Workshops, VDE-Verlag, (2011)A reusable IP FFT core for DSP applications., , , , , , and . ISCAS (3), page 621-624. IEEE, (2004)Understanding timing impact of BTI/RTN with massively threaded atomistic transient simulations., , , , and . ICICDT, page 1-4. IEEE, (2014)On the implementation of a baseband processor for a portable dual mode DECT/GSM terminal., , , and . ISCAS (4), page 334-337. IEEE, (2001)Accuracy of Quasi-Monte Carlo technique in failure probability estimations., , , , and . ICICDT, page 1-4. IEEE, (2016)A Framework for Interconnection-Aware Domain-Specific Many-Accelerator Synthesis., , , , and . ACM Trans. Embed. Comput. Syst., 16 (1): 8:1-8:26 (2016)GPU accelerated blockchain over key-value database transactions., , , , and . IET Blockchain, 2 (1): 1-12 (2022)Development and Testing on the European Space-Grade BRAVE FPGAs: Evaluation of NG-Large Using High-Performance DSP Benchmarks., , , , , , , and . IEEE Access, (2021)A novel methodology for designing high-performance and low-power FPGA interconnection targeting DSP applications., , and . ISCAS, IEEE, (2006)Designing Heterogeneous FPGAs with Multiple SBs., , , and . ARC, volume 4419 of Lecture Notes in Computer Science, page 91-96. Springer, (2007)