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Variable-Rate FEC Decoder VLSI Architecture for 400G Rate-Adaptive Optical Communication., , and . ICECS, page 45-48. IEEE, (2019)TinyVers: A Tiny Versatile System-on-chip with State-Retentive eMRAM for ML Inference at the Extreme Edge., , , , , and . CoRR, (2023)ZigZag: Enlarging Joint Architecture-Mapping Design Space Exploration for DNN Accelerators., , , , and . IEEE Trans. Computers, 70 (8): 1160-1174 (2021)Analyzing the Energy-Latency-Area-Accuracy Trade-off Across Contemporary Neural Networks., , and . AICAS, page 1-4. IEEE, (2021)CONVOLVE: Smart and seamless design of smart edge processors., , , , , , , , , and 18 other author(s). CoRR, (2022)Efficient Execution of Temporal Convolutional Networks for Embedded Keyword Spotting., , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (12): 2220-2228 (2021)Variable-Rate VLSI Architecture for 400-Gb/s Hard-Decision Product Decoder., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (1): 25-34 (2021)BitWave: Exploiting Column-Based Bit-Level Sparsity for Deep Learning Acceleration., , , , and . HPCA, page 732-746. IEEE, (2024)PATRONoC: Parallel AXI Transport Reducing Overhead for Networks-on-Chip targeting Multi-Accelerator DNN Platforms at the Edge., , , , , , , , and . DAC, page 1-6. IEEE, (2023)Enabling real-time object detection on low cost FPGAs., , and . J. Real Time Image Process., 19 (1): 217-229 (2022)