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Disambiguation of "Vamvakos, Socrates D."

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A 576 Mb DRAM with 16-channel 10.3125Gbps serial I/O and 14.5 ns latency.

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Socrates Linardakis

Socrates Varakliotis

Socrates Dimitriou-Zottos

Joana Sócrates-Dantas

D Böttger

 

Other publications of authors with the same name

Spurious-Free Time-to-Digital Conversion in an ADPLL Using Short Dithering Sequences., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 58-I (9): 2051-2060 (2011)6.3 A 10-to-112Gb/s DSP-DAC-Based Transmitter with 1.2Vppd Output Swing in 7nm FinFET., , , , , , , , , and 4 other author(s). ISSCC, page 120-122. IEEE, (2020)ADC-DSP-Based 10-to-112-Gb/s Multi-Standard Receiver in 7-nm FinFET., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 56 (4): 1265-1277 (2021)10-to-112-Gb/s DSP-DAC-Based Transmitter in 7-nm FinFET With Flex Clocking Architecture., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 56 (1): 30-42 (2021)A 8.125-15.625 Gb/s SerDes using a sub-sampling ring-oscillator phase-locked loop., , , , , , , , , and 7 other author(s). CICC, page 1-4. IEEE, (2014)Spurious free time-to-digital conversion in an ADPLL using short dithering sequences., , , , and . CICC, page 1-4. IEEE, (2010)A 576 Mb DRAM with 16-channel 10.3125Gbps serial I/O and 14.5 ns latency., , , , , , , , , and 29 other author(s). ESSCIRC, page 458-461. IEEE, (2012)An Intelligent RAM with Serial I/Os., , , , , , , , , and 1 other author(s). IEEE Micro, 33 (6): 56-65 (2013)A 2.488-11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications., , , , , , , , , and 7 other author(s). MWSCAS, page 5-8. IEEE, (2012)Discrete-Time, Linear Periodically Time-Variant Phase-Locked Loop Model for Jitter Analysis., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 58-I (6): 1211-1224 (2011)