Abstract
Low
-
density parity
-
check (LDPC) code, have become most popular, promising
near
-
optimal error correction code (ECC). Trade off between the performance and
complexity of LDPC decoders is of paramount interest to communication engineers and
researchers. The V
LSI implementation of LDPC decoder is a big challenge. VLSI
implementations has many difficulties to achieve as lower error floors, reduced interconnect
complexities, small chip areas, lower power dissipation to support multiple code lengths and
code rates . This Paper provides an overview of LDPC codes structure and different decoding algorithms.
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