Low
-
density parity
-
check (LDPC) code, have become most popular, promising
near
-
optimal error correction code (ECC). Trade off between the performance and
complexity of LDPC decoders is of paramount interest to communication engineers and
researchers. The V
LSI implementation of LDPC decoder is a big challenge. VLSI
implementations has many difficulties to achieve as lower error floors, reduced interconnect
complexities, small chip areas, lower power dissipation to support multiple code lengths and
code rates . This Paper provides an overview of LDPC codes structure and different decoding algorithms.
%0 Generic
%1 monica2014algorithms
%A Monica,
%A Mankar, V.
%A G.M.Asutkar,
%A and P.K.Dakhole,
%D 2014
%I ACEEE (A Computer division of IDES)
%K LDPC Min VLSI complexity etc implementation low sum
%T Algorithms and Architectures for Reduced Complexity LDPC Decoding: A survey
%U http://searchdl.org/public/conference/2014/ITC/97.pdf
%X Low
-
density parity
-
check (LDPC) code, have become most popular, promising
near
-
optimal error correction code (ECC). Trade off between the performance and
complexity of LDPC decoders is of paramount interest to communication engineers and
researchers. The V
LSI implementation of LDPC decoder is a big challenge. VLSI
implementations has many difficulties to achieve as lower error floors, reduced interconnect
complexities, small chip areas, lower power dissipation to support multiple code lengths and
code rates . This Paper provides an overview of LDPC codes structure and different decoding algorithms.
@conference{monica2014algorithms,
abstract = {Low
-
density parity
-
check (LDPC) code, have become most popular, promising
near
-
optimal error correction code (ECC). Trade off between the performance and
complexity of LDPC decoders is of paramount interest to communication engineers and
researchers. The V
LSI implementation of LDPC decoder is a big challenge. VLSI
implementations has many difficulties to achieve as lower error floors, reduced interconnect
complexities, small chip areas, lower power dissipation to support multiple code lengths and
code rates . This Paper provides an overview of LDPC codes structure and different decoding algorithms.},
added-at = {2014-03-24T06:02:48.000+0100},
author = {Monica and Mankar, V. and G.M.Asutkar and and P.K.Dakhole},
biburl = {https://www.bibsonomy.org/bibtex/2cc98b8118247826024b870eb6da045a1/idescitation},
interhash = {4b4438e579dee330f00c343f7a16ff25},
intrahash = {cc98b8118247826024b870eb6da045a1},
keywords = {LDPC Min VLSI complexity etc implementation low sum},
organization = {Institute of Doctors Engineers and Scientists},
publisher = {ACEEE (A Computer division of IDES)},
timestamp = {2014-03-24T06:02:48.000+0100},
title = {Algorithms and Architectures for Reduced Complexity LDPC Decoding: A survey},
url = {http://searchdl.org/public/conference/2014/ITC/97.pdf},
year = 2014
}