Reusable Test bench for Network on Chip Router using Advanced Verification Methodologies
International Journal of Innovative Science and Modern Engineering (IJISME), 1 (9):
70-74 (August 2013)Abstract
The focus of this Paper is the actual implementation of Reusable Network On Chip Router IP(Intellectual Property) and verifies the functionality of the five port IP router for System on chip applications using the latest verification methodologies(OVM,UVM,VMM) Hardware Verification Languages (Verilog, System Verilog),EDA tools. The Design of Network on Chip Router Implementing by using Verilog LRM as for Synthesis Environment. This Router design contains Four output ports and one input port, it is packet based Protocol. This Design consists of Registers, FSM and FIFO’s. The Verification goes on it finds functional coverage of the Network on Chip Router by using Verilog ,System Verilog using Questa-Sim 6.5e ,Synthesis is Xilinx ISE 9.2i EDA Tools.