%0 Journal Article %1 noauthororeditor %A Abid, Faroudja %A Izeboudjen, Nouma %D 2016 %J Informatics Engineering, an International Journal (IEIJ) %K ASIC; FPGA; OpenRISC; Opencores; SoC; VoIP %N 01 %P 01-09 %R DOI : 10.5121/ieij.2016.4102 %T FROM FPGA TO ASIC IMPLEMENTATION OF AN OPENRISC BASED SOC FOR VOIP APPLICATION %U http://aircconline.com/ieij/V4N1/4116ieij02.pdf %V 04 %X ASIC (Application Specific Integrated Circuit) design verification takes as long as the designers take to describe, synthesis and implement the design. The hybrid approach, where the design is first prototyped on an FPGA (Field-Programmable Gate Array) platform for functional validation and then implemented as an ASIC allows earlier defect detection in the design process and thus allows a significant time saving. This paper deals with a CMOS standard-cell ASIC implementation of a SoC (System on Chip) based on the OpenRISC processor for Voice over IP (VoIP) application; where a hybrid approach is adopted. The architecture of the design is mainly based on the reuse of IPs cores described at the RTL level. This RTL code is technology-independent; hence the design can be ported easily from FPGA to ASIC. Results show that the SoC occupied the area of 2.64mm². Regarding the power consumption, RTL power estimation is given.

@article{noauthororeditor, abstract = {ASIC (Application Specific Integrated Circuit) design verification takes as long as the designers take to describe, synthesis and implement the design. The hybrid approach, where the design is first prototyped on an FPGA (Field-Programmable Gate Array) platform for functional validation and then implemented as an ASIC allows earlier defect detection in the design process and thus allows a significant time saving. This paper deals with a CMOS standard-cell ASIC implementation of a SoC (System on Chip) based on the OpenRISC processor for Voice over IP (VoIP) application; where a hybrid approach is adopted. The architecture of the design is mainly based on the reuse of IPs cores described at the RTL level. This RTL code is technology-independent; hence the design can be ported easily from FPGA to ASIC. Results show that the SoC occupied the area of 2.64mm². Regarding the power consumption, RTL power estimation is given. }, added-at = {2018-08-23T11:01:45.000+0200}, author = {Abid, Faroudja and Izeboudjen, Nouma}, biburl = {https://www.bibsonomy.org/bibtex/219973cc8c0061885ffcd46c425bc6a9e/ieij1}, doi = {DOI : 10.5121/ieij.2016.4102}, interhash = {7f03e5be88ea071392a1e88d53f48327}, intrahash = {19973cc8c0061885ffcd46c425bc6a9e}, issn = {ISSN : 2349 - 2198}, journal = {Informatics Engineering, an International Journal (IEIJ)}, keywords = {ASIC; FPGA; OpenRISC; Opencores; SoC; VoIP}, language = {english}, month = mar, number = 01, pages = {01-09}, timestamp = {2018-08-23T11:01:45.000+0200}, title = {FROM FPGA TO ASIC IMPLEMENTATION OF AN OPENRISC BASED SOC FOR VOIP APPLICATION}, url = {http://aircconline.com/ieij/V4N1/4116ieij02.pdf}, volume = 04, year = 2016 }