%0 Conference Paper %1 10.1007/978-3-030-27562-4_1 %A Gesper, Sven %A Weißbrich, Moritz %A Nolting, Stephan %A Stuckenberg, Tobias %A Jääskeläinen, Pekka %A Blume, Holger %A Payá Vayá, Guillermo %B Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS) %C Cham %D 2019 %E Pnevmatikatos, Dionisios N. %E Pelcat, Maxime %E Jung, Matthias %I Springer International Publishing %K 2019 myown %P 3--17 %T Evaluation of Different Processor Architecture Organizations for On-site Electronics in Harsh Environments %X Microcontroller units used in harsh environmental conditions are manufactured using large semiconductor technology nodes in order to provide reliable operation, even at high temperatures or increased radiation exposition. These large technology nodes imply high gate propagation delays, drastically reducing the system's performance. When reducing area costs and power consumption, the actual processor architecture becomes a major design point. Depending on the application characteristics (i.e., inherent data parallelisms, type of arithmetic, ...), several parameters like data path width, instruction execution paradigm, or other architectural design mechanisms have to be considered. This paper presents a design space exploration of five different architectures implemented for a \$\$\0.18\\backslash,\\backslashupmu \backslashmathrm\m\\\$\$SOI CMOS technology for high temperature using an exemplary case study from the fields of communication, i.e., Reed-Solomon encoder. For this algorithm, an application-specific configuration of a transport-triggered architecture has 37.70x of the performance of a standard 8-bit microcontroller while the silicon area is increased by 4.10x. %@ 978-3-030-27562-4

@inproceedings{10.1007/978-3-030-27562-4_1, abstract = {Microcontroller units used in harsh environmental conditions are manufactured using large semiconductor technology nodes in order to provide reliable operation, even at high temperatures or increased radiation exposition. These large technology nodes imply high gate propagation delays, drastically reducing the system's performance. When reducing area costs and power consumption, the actual processor architecture becomes a major design point. Depending on the application characteristics (i.e., inherent data parallelisms, type of arithmetic, ...), several parameters like data path width, instruction execution paradigm, or other architectural design mechanisms have to be considered. This paper presents a design space exploration of five different architectures implemented for a {\$}{\$}{\{}0.18{\}}{\backslash},{\{}{\backslash}upmu {\backslash}mathrm{\{}m{\}}{\}}{\$}{\$}SOI CMOS technology for high temperature using an exemplary case study from the fields of communication, i.e., Reed-Solomon encoder. For this algorithm, an application-specific configuration of a transport-triggered architecture has 37.70x of the performance of a standard 8-bit microcontroller while the silicon area is increased by 4.10x.}, added-at = {2020-01-09T14:23:55.000+0100}, address = {Cham}, author = {Gesper, Sven and Wei{\ss}brich, Moritz and Nolting, Stephan and Stuckenberg, Tobias and J{\"a}{\"a}skel{\"a}inen, Pekka and Blume, Holger and Pay{\'a} Vay{\'a}, Guillermo}, biburl = {https://www.bibsonomy.org/bibtex/2e6c386da838a794cfdfb0e21f8dc1645/imsl3s}, booktitle = {Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)}, description = {Evaluation of Different Processor Architecture Organizations for On-site Electronics in Harsh Environments | SpringerLink}, editor = {Pnevmatikatos, Dionisios N. and Pelcat, Maxime and Jung, Matthias}, interhash = {77e4846f65c324b22bbec0c007ee2ce8}, intrahash = {e6c386da838a794cfdfb0e21f8dc1645}, isbn = {978-3-030-27562-4}, keywords = {2019 myown}, pages = {3--17}, publisher = {Springer International Publishing}, timestamp = {2020-01-21T13:29:24.000+0100}, title = {Evaluation of Different Processor Architecture Organizations for On-site Electronics in Harsh Environments}, year = 2019 }