%0 Journal Article %1 journals/jssc/ShahramianCV06 %A Shahramian, Shahriar %A Carusone, Anthony Chan %A Voinigescu, Sorin P. %D 2006 %J IEEE J. Solid State Circuits %K dblp %N 10 %P 2233-2240 %T Design Methodology for a 40-GSamples/s Track and Hold Amplifier in 0.18-$muhbox m$SiGe BiCMOS Technology. %U http://dblp.uni-trier.de/db/journals/jssc/jssc41.html#ShahramianCV06 %V 41

@article{journals/jssc/ShahramianCV06, added-at = {2022-01-03T00:00:00.000+0100}, author = {Shahramian, Shahriar and Carusone, Anthony Chan and Voinigescu, Sorin P.}, biburl = {https://www.bibsonomy.org/bibtex/2719287e43575a118f49aff6f60ceaf45/dblp}, ee = {https://doi.org/10.1109/JSSC.2006.878111}, interhash = {120474c290e873cf7fec11242181074b}, intrahash = {719287e43575a118f49aff6f60ceaf45}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 10, pages = {2233-2240}, timestamp = {2024-04-08T10:42:35.000+0200}, title = {Design Methodology for a 40-GSamples/s Track and Hold Amplifier in 0.18-$muhbox m$SiGe BiCMOS Technology.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc41.html#ShahramianCV06}, volume = 41, year = 2006 }