%0 Journal Article %1 journals/tvlsi/DattaBCMR08 %A Datta, Animesh %A Bhunia, Swarup %A Choi, Jung Hwan %A Mukhopadhyay, Saibal %A Roy, Kaushik %D 2008 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 7 %P 806-815 %T Profit Aware Circuit Design Under Process Variations Considering Speed Binning. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi16.html#DattaBCMR08 %V 16

@article{journals/tvlsi/DattaBCMR08, added-at = {2024-05-07T00:00:00.000+0200}, author = {Datta, Animesh and Bhunia, Swarup and Choi, Jung Hwan and Mukhopadhyay, Saibal and Roy, Kaushik}, biburl = {https://www.bibsonomy.org/bibtex/27ed9214e3346284f91679eb351ded2f2/dblp}, ee = {https://doi.org/10.1109/TVLSI.2008.2000364}, interhash = {901d70486afe9ad0a01156fc35cd3aed}, intrahash = {7ed9214e3346284f91679eb351ded2f2}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 7, pages = {806-815}, timestamp = {2024-05-13T07:13:35.000+0200}, title = {Profit Aware Circuit Design Under Process Variations Considering Speed Binning.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi16.html#DattaBCMR08}, volume = 16, year = 2008 }