Inproceedings,
15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips.
J. Su, X. Si, Y. Chou, T. Chang, W. Huang, Y. Tu, R. Liu, P. Lu, T. Liu, J. Wang, Z. Zhang, H. Jiang, S. Huang, C. Lo, R. Liu, C. Hsieh, K. Tang, S. Sheu, S. Li, H. Lee, S. Chang, S. Yu, and M. Chang.ISSCC, page 240-242. IEEE, (2020)
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- BibTeX key
- conf/isscc/SuSCCHTLLLWZJHL20
- entry type
- inproceedings
- booktitle
- ISSCC
- year
- 2020
- pages
- 240-242
- publisher
- IEEE
- crossref
- conf/isscc/2020
- ee
- https://doi.org/10.1109/ISSCC19947.2020.9062949
- isbn
- 978-1-7281-3205-1
- url
- http://dblp.uni-trier.de/db/conf/isscc/isscc2020.html#SuSCCHTLLLWZJHL20
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%1 conf/isscc/SuSCCHTLLLWZJHL20
%A Su, Jian-Wei
%A Si, Xin
%A Chou, Yen-Chi
%A Chang, Ting-Wei
%A Huang, Wei-Hsing
%A Tu, Yung-Ning
%A Liu, Ruhui
%A Lu, Pei-Jung
%A Liu, Ta-Wei
%A Wang, Jing-Hong
%A Zhang, Zhixiao
%A Jiang, Hongwu
%A Huang, Shanshi
%A Lo, Chung-Chuan
%A Liu, Ren-Shuo
%A Hsieh, Chih-Cheng
%A Tang, Kea-Tiong
%A Sheu, Shyh-Shyuan
%A Li, Sih-Han
%A Lee, Heng-Yuan
%A Chang, Shih-Chieh
%A Yu, Shimeng
%A Chang, Meng-Fan
%B ISSCC
%D 2020
%I IEEE
%K dblp
%P 240-242
%T 15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips.
%U http://dblp.uni-trier.de/db/conf/isscc/isscc2020.html#SuSCCHTLLLWZJHL20
%@ 978-1-7281-3205-1
@inproceedings{conf/isscc/SuSCCHTLLLWZJHL20,
added-at = {2024-05-07T00:00:00.000+0200},
author = {Su, Jian-Wei and Si, Xin and Chou, Yen-Chi and Chang, Ting-Wei and Huang, Wei-Hsing and Tu, Yung-Ning and Liu, Ruhui and Lu, Pei-Jung and Liu, Ta-Wei and Wang, Jing-Hong and Zhang, Zhixiao and Jiang, Hongwu and Huang, Shanshi and Lo, Chung-Chuan and Liu, Ren-Shuo and Hsieh, Chih-Cheng and Tang, Kea-Tiong and Sheu, Shyh-Shyuan and Li, Sih-Han and Lee, Heng-Yuan and Chang, Shih-Chieh and Yu, Shimeng and Chang, Meng-Fan},
biburl = {https://www.bibsonomy.org/bibtex/2b4c95ce39b69959e878be4f24af61fce/dblp},
booktitle = {ISSCC},
crossref = {conf/isscc/2020},
ee = {https://doi.org/10.1109/ISSCC19947.2020.9062949},
interhash = {4ed848290ed0751247f62a7492cef2e4},
intrahash = {b4c95ce39b69959e878be4f24af61fce},
isbn = {978-1-7281-3205-1},
keywords = {dblp},
pages = {240-242},
publisher = {IEEE},
timestamp = {2024-05-13T09:02:23.000+0200},
title = {15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips.},
url = {http://dblp.uni-trier.de/db/conf/isscc/isscc2020.html#SuSCCHTLLLWZJHL20},
year = 2020
}