%0 Generic %1 amiri2021flower %A Amiri, Puya %A Pérard-Gayot, Arsène %A Membarth, Richard %A Slusallek, Philipp %A Leißa, Roland %A Hack, Sebastian %D 2021 %K Compiler Dataflow FPGA HLS %R 10.1109/ICFPT52863.2021.9609930 %T FLOWER: A comprehensive dataflow compiler for high-level synthesis %U http://arxiv.org/abs/2112.07789 %X FPGAs have found their way into data centers as accelerator cards, making reconfigurable computing more accessible for high-performance applications. At the same time, new high-level synthesis compilers like Xilinx Vitis and runtime libraries such as XRT attract software programmers into the reconfigurable domain. While software programmers are familiar with task-level and data-parallel programming, FPGAs often require different types of parallelism. For example, data-driven parallelism is mandatory to obtain satisfactory hardware designs for pipelined dataflow architectures. However, software programmers are often not acquainted with dataflow architectures - resulting in poor hardware designs. In this work we present FLOWER, a comprehensive compiler infrastructure that provides automatic canonical transformations for high-level synthesis from a domain-specific library. This allows programmers to focus on algorithm implementations rather than low-level optimizations for dataflow architectures. We show that FLOWER allows to synthesize efficient implementations for high-performance streaming applications targeting System-on-Chip and FPGA accelerator cards, in the context of image processing and computer vision.

@conference{amiri2021flower, abstract = {FPGAs have found their way into data centers as accelerator cards, making reconfigurable computing more accessible for high-performance applications. At the same time, new high-level synthesis compilers like Xilinx Vitis and runtime libraries such as XRT attract software programmers into the reconfigurable domain. While software programmers are familiar with task-level and data-parallel programming, FPGAs often require different types of parallelism. For example, data-driven parallelism is mandatory to obtain satisfactory hardware designs for pipelined dataflow architectures. However, software programmers are often not acquainted with dataflow architectures - resulting in poor hardware designs. In this work we present FLOWER, a comprehensive compiler infrastructure that provides automatic canonical transformations for high-level synthesis from a domain-specific library. This allows programmers to focus on algorithm implementations rather than low-level optimizations for dataflow architectures. We show that FLOWER allows to synthesize efficient implementations for high-performance streaming applications targeting System-on-Chip and FPGA accelerator cards, in the context of image processing and computer vision.}, added-at = {2021-12-16T16:46:08.000+0100}, author = {Amiri, Puya and Pérard-Gayot, Arsène and Membarth, Richard and Slusallek, Philipp and Leißa, Roland and Hack, Sebastian}, biburl = {https://www.bibsonomy.org/bibtex/2a47172a1974839b29735df9f2aa24205/pooya_ww}, description = {FLOWER: A comprehensive dataflow compiler for high-level synthesis}, doi = {10.1109/ICFPT52863.2021.9609930}, interhash = {4fcad487f6981c3022ab5e0c2db8d9c1}, intrahash = {a47172a1974839b29735df9f2aa24205}, keywords = {Compiler Dataflow FPGA HLS}, note = {cite arxiv:2112.07789}, timestamp = {2021-12-16T16:46:08.000+0100}, title = {FLOWER: A comprehensive dataflow compiler for high-level synthesis}, url = {http://arxiv.org/abs/2112.07789}, year = 2021 }